How to Make PN Junction of InSb Photosensitive Chip?

insb wafer

How to Make PN Junction of InSb Photosensitive Chip?

In terms of mid-infrared detection in the 3-5um band, detectors based on InSb materials stand out from many material devices due to their mature material technology, high sensitivity, and good stability. InSb has become the preferred material for the preparation of mid-wave infrared detectors. Ganwafer can supply InSb wafers for infrared detectors, more specifications please view:; or send your enquiries to As a direct bandgap semiconductor material, InSb has small electron effective mass, high mobility and narrow band gap (0.17eV at 300K and 0.23eV at 77K). At low temperature, InSb has a high absorption coefficient for infrared light (~1014cm-1), a quantum efficiency greater than or equal to 80%, and a high carrier mobility (un~105cm2∙V-1∙s-1).

With the continuous development of infrared detection technology, photosensitive chips based on InSb materials have experienced the development process from unit chips to multi-element, line array and area array chips. After the flip-chip interconnection process, the photosensitive chip and the signal processing circuit are combined together and placed on the focal plane of the optical system, which constitutes the core component of infrared signal detection. In the realization of photoelectric conversion, the performance of the InSb photosensitive chip is one of the key factors that determine the detection level of the focal plane detector. In the preparation of the InSb area array photosensitive chip, the quality of the PN junction and the effective isolation of the photosensitive pixel units are the core keys to the preparation of the area array chip. Among them, the preparation process of the PN junction is divided into a diffusion process, an ion implantation process and an epitaxy process, which are mainstream technologies for fabricating InSb infrared detector. For different PN junction fabrication techniques, the corresponding surface array structure fabrication techniques are also different. The manufacturing technology of the photosensitive chip is introduced according to PN junction preparation processes.

1. Thermal Diffusion Process

The thermal diffusion process is the first developed and mature process method. The principle of the process is to obtain enough energy for the doping element atoms to enter the indium antimonide crystal and occupy the lattice vacancies through the method of high temperature heating, so as to realize the element doping and material modification. The diffusion process technology is mature and the equipment is simple, but the control ability of doping impurities is poor. Therefore, the repeatability between batches and between InSb substrates in the same batch is relatively poor, and the uniformity control of large-area array diffusion is poor; there is serious lateral diffusion during the vertical incorporation of impurity elements into the material, as shown in the figure 1. Therefore, in the preparation of an InSb area array photosensitive chip, it is usually necessary to use a wet etching technique or a dry etching technique to prepare a mesa junction focal plane array (FPA).

Effect Diagram of Lateral Diffusion

Fig. 1 Effect Diagram of Lateral Diffusion

2. Ion Implantation Process

The ion implantation process was born out of the need for higher performance PN junctions. The implantation process ionizes the impurity elements into high-energy particles through the ion source components of the equipment, and implants high-energy ions with high energy of up to kilograms and trillions into the substrate material through pipelines such as acceleration tubes, so as to realize the doping of material components and change the material properties. It can be known from the process realization process and process principle that in the process of doping the substrate material in the diffusion process, the doping concentration on the surface of the material is the highest. As the doping depth deepens, the doping concentration gradually decreases, and the diffusion process becomes a graded junction. During the junction formation process of the implantation process, the high-energy particles are hindered by nuclei and internuclear electrons after being implanted into the substrate material, and gradually decelerate and stay at a certain depth. Implant the highest concentration at a location in the implant range other than the surface of the substrate material. The distribution of implanted elements is relatively concentrated, and the formed PN junction is an abrupt junction structure. If the process is properly designed, a PN junction with excellent performance can be obtained and the noise current of the device can be reduced.

Ion Implantation

Fig. 2 Schematic Diagram of Ion Implantation

For the preparation of InSb based infrared photosensitive chips, the advantage of the ion implantation process is that the implantation energy and dose can be freely controlled, and the quantity and depth of implanted impurities can be precisely controlled, so as to achieve extremely low and shallow junction implantation. The implanted impurities are almost vertically incident into the base material according to the mask pattern, and there will be no serious lateral diffusion; the equipment is highly automated, which can achieve uniform doping in a large area, with good repeatability, ensuring the accuracy and repeatability of doping. A single impurity can be accurately selected to ensure the purity of the doping element. Compared with the diffusion process, the ion implantation process does not require high temperature treatment, and the process time is shorter than the diffusion process, which can effectively improve the production efficiency of InSb photosensitive chips.

In view of the advantages of vertical doping collimation of ion implantation, the structure of the area array photosensitive chip matched with the ion implantation process is generally a planar junction structure. The ion implantation process combined with the planar junction structure has following advantages:

1) Reduce process steps such as photolithography, corrosion, and etching processes involved in pixel isolation;

2) The integrity of the photosensitive surface array is better, bubbles are not easy to appear in the later interconnection and dispensing process, and the stress response ability is stronger in the process of grinding, polishing and thinning;

3) There is no need to prepare a groove structure to achieve pixel isolation, which can reduce the pixel center distance and reduce the size of InSb area array chip. Thereby, the size of the supporting Dewar and refrigeration structure is reduced, and the power consumption and cost are reduced.

3. InSb Epitaxy Process

Judging from the performance exhibited by the current epitaxial films, epitaxy is a promising InSb focal plane array fabrication technology. Epitaxial growth is a preparation technology of growing a new single crystal layer according to the original crystal orientation on a single crystal InSb substrate whose surface has been carefully processed at a temperature lower than the melting point of the crystal. An important feature of epitaxial technology is that during the preparation of the InSb epitaxial crystal layer, the impurity concentration in the layer can be adjusted by controlling the impurity content in the reaction, which is not affected by the type of substrate and the impurity doping level. Therefore, when the PN junction is formed by this technique, the impurity distribution can be close to the ideal abrupt impurity distribution. Commonly used epitaxy process methods include MBE, MOCVD, LPE and MSE etc.

Growth Principle of MBE Epitaxial Layer

Fig. 3 Schematic Diagram of the Growth Principle of MBE Epitaxial Layer

The epitaxial process can provide more advanced device structures. The advantage of epitaxial technology is that the conductivity type of the grown semiconductor can be controlled on demand during the InSb epitaxial crystallization process, and the doping amount of impurities can be adjusted at any time. It has uniform growth, in-situ doping, real-time control, and no need to reduce Due to the advantages of thinness and other advantages, different device structures can be designed and fabricated by controlling the device parameters in the epitaxy process, so as to realize the fabrication of high-temperature working devices and dual-polychromatic band working devices.

Since the epitaxial process adopts the whole-chip growth method, it can only be used for the preparation of mesa junction structure devices.

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